USB host controller with memory for transfer descriptors

ABSTRACT

An electronic device, operating as a USB host, has an embedded processor and a system memory, connected by a memory bus. A host controller integrated circuit does not need to master the system memory, but instead acts purely as a slave. The embedded processor is then adapted to write the data to the host controller integrated circuit in the form of transfer-based transactions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage application of Patent CooperationTreaty (PCT) Application No. PCT/IB2004/050640 filed May 12, 2004, whichin turn claims priority from PCT/SG03/00128 filed May 15, 2003, thecontents of which are incorporated by reference herein.

TECHNICAL FIELD

This invention relates to a bus system, and in particular to a buscontroller, and to a device incorporating the bus controller.

More particularly, the invention relates to an integrated circuit whichcan be used as a host controller within an electronic device, in orderto improve the efficiency of operation of the device.

BACKGROUND INFORMATION

In a conventional electronic device, operating as a USB host, theprocessor is able to write data into a system memory. A host controllerintegrated circuit is then able to read the data directly from thesystem memory. In order to be able to do this, the host controller needsto master the system memory. However, since the system memory is sharedbetween the host controller integrated circuit and the system processor,this requirement that the host controller be able to master the systemmemory requires the use of a bus master, which is specific to the systemprocessor. Moreover, while the host controller is mastering the systemmemory, the core function of the device, running under the control ofthe system processor, may be disrupted.

BRIEF SUMMARY

According to an aspect of the present invention, a host controllerintegrated circuit is unable to master the system memory, but insteadacts purely as a slave. The embedded processor is then adapted to writethe data to the host controller integrated circuit in the form oftransfer-based transactions.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention will be described with reference to the accompanyingdrawings in which:

FIG. 1 is a block schematic diagram of a USB host in accordance with anaspect of the present invention.

FIG. 2 is a block schematic diagram of a host controller in accordancewith another aspect of the invention.

FIG. 3 is a block schematic diagram of an alternative form of hostcontroller in accordance with an aspect of the invention.

FIG. 4 illustrates the structure of the memory in the host controller ofFIG. 2 or FIG. 3.

FIG. 5 is an illustration showing the format of software in the deviceof FIG. 1.

FIG. 6 illustrates the format of data written from the hostmicroprocessor to the host controller.

FIG. 7 shows the structure of a transfer descriptor header, with whichdata is transferred.

FIG. 8 is a schematic representation of data to be transmitted, storedin the memory of FIG. 4.

FIG. 9 illustrates a method by which the data of FIG. 8 may betransmitted.

DETAILED DESCRIPTION

FIG. 1 is a block schematic diagram of the relevant parts of anelectronic device 10, operating as a USB host. The invention isparticularly applicable to devices such as mobile phones, or PDAs, inwhich the functional limitations of the microprocessor and the systemmemory are more relevant, rather than in personal computers (PCs).However, the invention is applicable to any device which can operate asa USB host.

It will be apparent that the device 10 will have many features, whichare not shown in FIG. 1, since they are not relevant to an understandingof the present invention.

The device 10 has a host microprocessor 20, which includes a processorcore 22, connected by a standard system bus 23 to a LCD controller 24, aDMA master 25, and a memory controller 26. The memory controller 26 isconnected to a system memory 30 by means of a peripheral bus 32.

A host controller 40 is also connected to the host microprocessor 20 andthe system memory 30, by means of the peripheral bus, or memory bus, 32.The host controller 40 has an interface for a USB bus 42, through whichit can be connected to multiple USB devices. In this illustratedembodiment, the host controller 40 is a USB 2.0 host controller.

As is conventional, the host controller 40 is adapted to retrieve datawhich is prepared by the processor 20 in a suitable format, and totransmit the data over the bus interface. In USB communications, thereare two categories of data transfer, namely asynchronous transfer andperiodic transfer. Control and bulk data are transmitted usingasynchronous transfer, and ISO and interrupt data are transmitted usingperiodic transfer. A Queue Transaction Descriptor (qTD) data structureis used for asynchronous transfer, and an Isochronous TransactionDescriptor (iTD) data structure is used for periodic transfer.

The processor 20 prepares the data in the appropriate structure, andstores it in the system memory 30, and the host controller 40 must thenretrieve the data from the system memory 30.

FIG. 2 shows in more detail the structure of the embedded USB hostcontroller 40.

As mentioned above, the host controller 40 has a connection for thememory bus 32, which is connected to an interface 44, containing aMemory Mapped Input/Output, a Memory Management Unit, and a Slave DMAController. The interface 44 also has a connection 46 for control andinterrupt signals, and registers 48 which support the RAM structure andthe operational registers of the host controller 40.

The interface 44 is connected to the on-chip RAM 50 of the hostcontroller, which in this preferred embodiment is a dual port RAM, aswill be described in more detail below. The memory 50 is connected tothe host controller logic unit 52, which also contains an interface forthe USB bus 42. Control signals can be sent from the registers 48 to thelogic unit 52 on an internal bus 54.

As mentioned above, the on-chip memory 50 in this case is a dual portRAM, allowing data to be written to and read from the memorysimultaneously.

FIG. 3 shows an alternative embodiment of the invention, in which commonreference numerals indicate the same features as in FIG. 2. In thiscase, the on-chip memory 56 is a single port RAM, and data written toand read from the memory 56 is transferred through an arbiter 58, whichagain allows for effectively simultaneous access to the memory 56.

FIG. 4 shows the structure of the on-chip memory. As far as thestructure shown in FIG. 4 is concerned, this is the same whether theon-chip memory is the dual port RAM 50 shown in FIG. 2, or the singleport RAM 56 shown in FIG. 3.

As shown in FIG. 4, the RAM is effectively divided into two parts,namely a first part 70 which contains header and status information forthe stored transfer descriptors TD1, TD2, . . . , TDn, and which isitself subdivided into a portion 72 relating to asynchronous (bulk)transfers and a portion 74 relating to periodic (isochronous andinterrupt) transfers, and a second part 76, which contains the payloaddata for those stored transfer descriptors TD1, TD2, . . . , TDn.

This structure of the RAM has the advantage that the host microprocessor20 an easily write and read all of the transfer descriptor headerstogether. This structure also makes it easy for the headers relating toperiodic transfers to be scanned only once in each micro-frame, whileheaders relating to asynchronous transfers are scanned continuouslythroughout the micro-frame.

This means that the time between transactions will be small and, equallyimportantly, it will be consistent from one transaction to another.

FIG. 5 is a schematic diagram showing in part the software operating onthe host controller 40, in order to illustrate the method of operationof the device according to the invention.

The host controller 40 runs USB driver software 80 and USB Enhanced HostController Interface software 82, which are generally conventional.

However, in accordance with the present invention, the host controller40 also runs USB EHCI interface software 84, which prepares a list oftransfer-based transfer descriptors for every endpoint to which data isto be transmitted.

The EHCI interface software 84 is written such that it uses theparameters which are generated by the EHCI host stack 82 for theexisting periodic and asynchronous headers, and can be used for alldifferent forms of USB transfer, in particular high speed USB transfer,such as high speed isochronous, bulk, interrupt and control andstart/stop split transactions.

The host microprocessor 20 writes the transfer-based transferdescriptors into the RAM 50 or 56 of the host controller 40 through theperipheral bus 32, without the host controller 40 requiring to masterthe bus 32. In other words, the host controller 40 acts only as a slave.The transfer-based transfer descriptors can then be memory-mapped intothe RAM 50 or 56 of the host controller 40.

Advantageously, the built-in memory 50 or 56 of the host controller 40is mapped in the host microprocessor 20, improving the ease with whichtransactions can be scheduled from the host microprocessor 20.

Moreover, as described above, the use of a dual-port RAM 50, or asingle-port RAM 56 plus an arbiter 58, means that, while onetransfer-based transfer descriptor is being executed by the hostcontroller 40, the host microprocessor 20 can be writing data intoanother block space.

FIG. 6 illustrates the format of one USB frame, divided into multiplemicro-frames, in which data is transmitted from the host controller 40over the USB bus 42. As is conventional, multiple transactions,including transactions of different transfer types, may be sent withinone micro-frame. Again, as is conventional, high speed isochronoustransfer is always first, followed by high speed interrupt transfer, andfull speed and low speed Start Split and Complete Split transfers, withhigh speed bulk data occupying the remaining time in the micro-frame.

The transfer-based protocol allows the host microprocessor 20 to write a1 ms frame of data into the RAM 50 or 56 of the host controller(provided that the RAM is large enough to hold this data), such thatthis can be transmitted over the USB bus 42 without further interventionfrom the host microprocessor 20.

FIG. 7 illustrates the transfer-based protocol for supporting high-speedUSB transmissions, with FIG. 7 a showing the format of a 16-byte headerof a transfer-based transfer descriptor for one endpoint, in accordancewith the protocol, and FIGS. 7 b and 7 c describing the contents of theheader fields. The transfer-based protocol header consists of parametersthat have the same definition as the conventional USB EHCI software,allowing the transfer descriptors to be easily constructed.

The transfer-based protocol also ensures that data can be sent to eachUSB endpoint on a fair basis.

FIG. 8 shows a situation in which the payload data associated with afirst transfer descriptor TD1 is divided into three packets, PL1, PL2and PL3, each of 64 bytes; the payload data associated with a secondtransfer descriptor TD2 comprises just one packet PL1 of 32 bytes; thepayload data associated with a third transfer descriptor TD3 is dividedinto two packets PL1 and PL2, each of 8 bytes; and the payload dataassociated with a fourth transfer descriptor TD4 is divided into fourpackets PL1, PL2, PL3 and PL4, each of 16 bytes.

FIG. 9 illustrates the method by which these packets of data aretransferred out of the RAM 50, or 56, to their respective endpoints inrespective devices connected to the host.

As indicated by the arrow 90 in FIG. 8, a cyclical process occurs.Firstly, in step 91, the first packet PL1 associated with the firsttransfer descriptor TD1 is transferred. The transfer descriptor containsan Active flag which is set high, to indicate that there remains moredata associated with this transfer descriptor.

Secondly, in step 92, the first packet PL1 associated with the secondtransfer descriptor TD2 is transferred. This transfer descriptor nowcontains an Active flag which is set low by the host controller 40,indicating that this completes the transfer of the payload dataassociated with the second transfer descriptor TD2.

Next, in steps 93 and 94, the first packets PL1 of payload dataassociated with the third and fourth transfer descriptors TD3 and TD4respectively, are transferred. Again, each of these transfer descriptorscontain an Active flag which is set high, indicating that there is moreof the payload data associated with each of the transfer descriptors,remaining to be transferred.

Next, in step 95, the second packet PL2 of payload data associated withthe first transfer descriptor TD1 is transferred. The Active flagremains high, because there is still more of the payload data associatedwith that transfer descriptor, remaining to be transferred.

The transfer of the payload data associated with the second transferdescriptor TD2 has been completed, and so, in step 96, the second packetPL2 of payload data associated with the third transfer descriptor TD3 istransferred. This time, the Active flag in this transfer descriptor isset low, indicating that this completes the transfer of the payload dataassociated with the third transfer descriptor TD3.

In step 97, the second packet PL2 of payload data associated with thefourth transfer descriptor TD4 is transferred, and the Active flagremains high.

In step 98, the third packet PL3 of payload data associated with thefirst transfer descriptor TD1 is transferred, and the Active flag is setlow, indicating that this completes the transfer of payload dataassociated with the first transfer descriptor.

In steps 99 and 100, the third and fourth packets PL3 and PL4 of payloaddata associated with the fourth transfer descriptor TD4 are transmitted,with the Active flag being set low in step 100, to indicate that thiscompletes the transfer of the payload data associated with the fourthtransfer descriptor TD4.

During execution of the transfer-based transfer descriptors, the contentof the transfer-based transfer descriptors is updated by the hostcontroller logic unit 52. For example, the Active flag within a transferdescriptor header is set low when the transfer of the payload dataassociated with the transfer descriptor is completed. The USB EHCIinterface software 84 then reformats the updated transfer-based transferdescriptors into a format which can be handled by the conventional EHCIhost stack 82, and the updated transfer-based transfer descriptors arecopied back to the system memory 30.

There is therefore provided a host controller which allows theincorporation of high speed USB host functionality, in particular intonon-PC based systems.

1. A host controller for use in a bus communication device having a hostmicroprocessor and a system memory, the host controller comprising: afirst interface for direct connection to a memory bus which connects thehost microprocessor and the system memory, such that the host controlleris adapted to act only as a slave on the memory bus; an internal memoryconfigured into at least two distinct sections to store a plurality oftransfer-based transfer descriptors including a first section configuredto store a plurality of transfer-based transfer descriptor headers, anda second section configured to store a plurality of transfer-basedtransfer descriptor payloads, the respective transfer-based transferdescriptors received through the first interface, said internal memoryhaving a plurality of transfer-based transfer descriptor header andtransfer-based transfer descriptor payload locations mapped in the hostmicroprocessor, said first section of the internal memory is sub-dividedinto two sub-parts, and is adapted to consecutively store transferdescriptor headers relating to periodic transfers in a first subpart,and to consecutively store transfer descriptor headers relating toasynchronous transfers in a second sub-part; and a second interface, forconnection to an external bus, wherein the host controller is adaptedto: execute stored transfer-based transfer descriptors; update thecontent of the stored transfer-based transfer descriptors on execution;and copy the updated stored transfer-based transfer descriptors to thesystem memory.
 2. A host controller as claimed in claim 1, wherein theinternal memory is a dual-port RAM.
 3. A host controller as claimed inclaim 1, wherein the internal memory is a single-port RAM, and the hostcontroller further comprises an arbiter to allow data to be written toand read from the RAM essentially simultaneously.
 4. A host controlleras claimed in claim 1, wherein the host controller is adapted to scanthe first sub-part of the internal memory once in each micro-frame, andis adapted to scan the second sub-part continuously throughout eachmicro-frame.
 5. A host controller as claimed in claim 1, wherein thehost controller is a USB host controller and the second interface is aUSB bus interface.
 6. A host controller as claimed in claim 1, whereinthe internal memory is adapted to store multiple micro-frames oftransfer descriptors, and to execute the stored transfer descriptorswithout intervention from the host microprocessor.
 7. A host controlleras claimed in claim 6, wherein each of the multiple micro-frames oftransfer descriptors may store payload data relating to one or more ofisochronous, interrupt and bulk data transfers.
 8. A host controller asclaimed in claim 1, wherein the first interface comprises: a memorymapped input/output; a memory management unit; and a slave direct memoryaccess (DMA) controller.
 9. A host controller as claimed in claim 1,wherein the first interface comprises registers.
 10. A host controlleras claimed in claim 9, further comprising a logic unit, wherein thelogic unit comprises the second interface.
 11. A host controller asclaimed in claim 10, further comprising an internal bus coupled betweenthe registers and the logic unit, wherein the internal bus is configuredto carry control signals from the registers to the logic unit.
 12. Ahost controller as claimed in claim 1, further comprising an externalconnection to the first interface, wherein the external connection isconfigured to carry control and interrupt signals.
 13. The hostcontroller as claimed in claim 1 wherein the host controller is furtherconfigured to respond to memory transactions scheduled by the hostmicroprocessor.
 14. A bus communication device, comprising: a hostmicroprocessor; a system memory; a memory bus, which connects the hostmicroprocessor and the system memory; and a host controller, wherein thehost microprocessor is adapted to form transfer-based transferdescriptors, and write the transfer-based transfer descriptors to thesystem memory and to the host controller, and wherein the hostcontroller comprises: a first interface for direct connection to thememory bus, such that the host controller is adapted to act only as aslave on the memory bus; an internal memory, for storing a plurality oftransfer-based transfer descriptors, the internal memory having a firstsection adapted to consecutively store transfer descriptor headers and asecond section adapted to consecutively store transfer descriptorpayloads, the first section sub-divided into a first subpart adapted toconsecutively store transfer descriptor headers relating to periodictransfers and a second subpart adapted to consecutively store transferdescriptor headers relating to asynchronous transfers, the transferdescriptors received through the first interface, said internal memoryhaving a plurality of header and payload transfer descriptor locationsmapped in the host microprocessor; and a second interface, forconnection to an external bus, wherein the host controller is adaptedto: execute stored transfer-based transfer descriptors; update thecontent of the stored transfer-based transfer descriptors on execution;and copy the updated stored transfer-based transfer descriptors to thesystem memory.
 15. A bus communication device as in claim 14, whereinthe second interface for the host controller is a USB bus interface, andthe bus communication device is adapted to act as a USB host.
 16. A buscommunication device as claimed in claim 14, wherein the hostmicroprocessor is adapted to write a plurality of micro-frames oftransfer descriptors to the system memory and to the host controller,and the host controller is adapted to execute the plurality ofmicro-frames of transfer descriptors without intervention from the hostmicroprocessor.
 17. A bus communication device as claimed in claim 14,wherein the host controller further comprises: a memory mappedinput/output; a memory management unit; a slave direct memory access(DMA) controller; and registers.
 18. A bus communication device asclaimed in claim 17, wherein the host controller further comprises: alogic unit, wherein the logic unit comprises the second interface; andan internal bus coupled between the registers and the logic unit,wherein the internal bus configured to carry control signals from theregisters to the logic unit.
 19. A bus communication device as claimedin claim 14, wherein the host controller further comprises an externalconnection to the first interface, wherein the external connection isconfigured to carry control and interrupt signals.
 20. The buscommunication device as claimed in claim 14, wherein the plurality oflocations of the internal memory mapped to the system memory areconfigured for access by the host microprocessor when the hostmicroprocessor addresses the mapped addresses of the system memory. 21.A method of executing bus transactions with a host controllercomprising: configuring the host controller as a slave on a memory bus,the memory bus directly connected to the host controller, a hostmicroprocessor, and a system memory; configuring a block of dedicatedtransfer descriptor header space of an internal memory to be mappable inthe host microprocessor, said address space accessible via the memorybus; configuring a block of dedicated transfer descriptor payloadaddress space of an internal memory to be mappable in the hostmicroprocessor, wherein said address space accessible via the memorybus, wherein the block of dedicated transfer descriptor header addressspace is separate from the block of dedicated transfer descriptorpayload address space, and wherein the block of dedicated transferdescriptor header address space is sub-divided into a first subpartadapted to consecutively store transfer descriptor headers relating toperiodic transfers and a second subpart adapted to consecutively storetransfer descriptor headers relating to asynchronous transfers; readingtransfer-based transfer descriptors from the internal memory; executingthe transfer-based transfer descriptors; and updating the content of thetransfer-based transfer descriptors on execution.